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QL5332 QuickPCI Data Sheet
* * * * * * 33 MHz/32-Bit PCI Master/Target with Embedded
Programmable Logic and Dual Port SRAM
Device Highlights
High Performance PCI Controller
QL5332 supports new enhanced features added to QL5032: * All PCI commands (including configuration and MWI) * Fully-customizable byte enables as a master * Zero-wait-state write and one-wait-state read Target interface * Target interface supports retry, disconnect with/without data transfer, and target abort * Target aborts * Has 125 more logic cells in FPGA section, but 2 less RAM blocks * Pin compatible with QL5032 QL5332 also supports the original features of QL5032: * 32-bit/33 MHz PCI Master/Target * Zero-wait state PCI Master provides 132 MBps transfer rates * Programmable back-end interface to optional local processor * Independent PCI bus (33 MHz) and local bus (up to 160 MHz) clocks * Fully customizable PCI configuration space * Configurable FIFOs with depths up to 256 * Reference design with driver code (Win 95/98/2000/NT4.0) available * PCI v2.2 compliant * Supports Type 0 configuration cycles in Target mode * 3.3 V, 5 V tolerant PCI signaling supports universal PCI adapter designs * 3.3 V CMOS in 208-pin PQFP and 256-pin PBGA * Supports endian conversions * Unlimited/continuous burst transfers supported
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Extendable PCI Functionality
* Support for configuration space from 0x40 to 0x3FF * Multi-function, expanded capabilities, and expansion ROM capable * Power management, compact PCI, hotswap/hot-plug compatible * PCI v2.2 Power Management Spec compatible * PCI v2.2 Vital Product Data (VPD) configuration support
Programmable logic
* 515 logic cells * 13,824 RAM bits, up to 154 I/O pins * 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOs * All back-end interface and glue-logic can be implemented on chip * Any combination of FIFOs that require 12 or less QuickLogic RAM modules * Six 32-bit busses interface between the PCI Controller and the Programmable Logic Figure 1: QL5332 Block Diagram
PCI Bus 33 MHz/32 bits (data and address)
PCI Controller
Master Controller
High Speed Data Path
Target Controller
32 bit Interface Programmable Logic
Config. Space High Speed Logic Cells DMA Controller
154 User I/O
160 MHz FIFOs
PCI Bus
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QL5332 QuickPCI Data Sheet Rev. C
Architecture Overview
The QL5332 device in the QuickLogic QuickPCI Embedded Standard Product (ESP) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps). The programmable logic portion of the device contains 515 QuickLogic logic cells and 12 QuickLogic dualport RAM blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs. See RAM Module Features on page 9 for more information. The QL5332 device meets PCI v2.2 electrical and timing specifications and has been fully hardware-tested. The QL5332 device features 3.3 V operation with multi-volt compatible I/Os. Therefore, it can easily operate in 3 V systems and is fully compatible with 3.3 V, 5 V or Universal PCI card applications.
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI v2.2 compliant Master/Target Controller. It is capable of infinite length Master Write and Read transactions at zero-wait-states (132 MBps). The Master will never insert waitstates during transfers, so data must be supplied or received by FIFOs, which can be configured in the programmable region of the device. The Master is capable of initiating any type of PCI command, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL5332 device to act as a PCI host. The Master Controller is most often operated by a DMA Controller in the programmable region of the device. A DMA Controller reference design is available. The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-waitstate Target write and one-wait-state Target read operations. It also supports retry, disconnect with/without data transfer, and target abort requested by the backend. Any number of 32-bit BARs may be configured as memory or I/O space. All required and optional PCI v2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided. The interface ports are divided into a set of ports for Master transactions and a set for Target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be minimized.
PCI Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5332. QuickLogic provides a reference Address Register/Counter and Command Decode block.
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QL5332 QuickPCI Data Sheet Rev. C
DMA Master/Target Control
The customizable DMA controller included with the QuickWorks design software contains the following features: * Configurable DMA count size for Reads and Writes (up to 30-bits) * Configurable DMA burst size for PCI (including unlimited/continuous burst) * Customizable PCI command to use by core * Customizable Byte Enable signal * Programmable Arbitration between DMA Read & Write transactions * DMA Registers may be mapped to any area of Target Memory Space Read Address (32-bit register) Write Address (32-bit register) Read Length (16-bit register) / Write Length (16-bit register) Control and Status (32-bit register, includes 8 bit Burst Length) * DMA Registers are available to the local design or the PCI bus * Programmable Interrupt Control to signal end of transfer or other event
Configurable FIFOs
QuickWorks SpDE has a Creation Wizard that is used to create FIFOs. FIFOs may be designed up to 256 deep. Using the 12 QuickLogic RAM modules, the combinations include: * 6 FIFOs at 64 deep (36 wide) * 3 FIFOs at 128 deep (36 wide) * 1 FIFO at 256 deep (48 wide)
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QL5332 QuickPCI Data Sheet Rev. C
PCI Interface Symbol
Figure 2 shows the interface symbol to use in the schematic design to attach the local interface programmable logic design to the PCI core. This symbol is used in schematic or mixed schematic/HDL design flows in the QuickWorks software. If designing with a top-level Verilog or VHDL file, use a structural instantiation of this PCI32N block, instead of a graphical symbol. Figure 2: PCI Interface Symbol
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QL5332 QuickPCI Data Sheet Rev. C
Internal Port Descriptions
Signals that end with the character 'N' should be considered active-low (for example, Mst_IRDYN). 'I' indicates that it is an input to the core, 'O' indicates it is an output of the core, and 'B' indicates it is a bi-directional signal (only on PCI pins).
Master Interface Signals
The master interface signals for QL5332 PCI32N are shown in Table 1. Table 1: QL5332 PCI32N Master Interface Signals
Signal Type Description PCI command to be used for the master transaction. This signal must remain unchanged throughout the period when Mst_Burst_Req is active. PCI commands considered as reads include: '0000' Interrupt Acknowledge '0010' I/O Read '0110' Memory Read '1010' Configuration Read '1100' Memory Read Multiple '1110' Memory Read Line PCI commands considered as writes include: '0001' Special Cycle '0011' I/O Write '0111' Memory Write '1011' Configuration Write '1111' Memory Write and Invalidate Users should make sure that only valid PCI commands are supplied. Request use of the PCI bus. When it is active, the core requests the PCI bus and once granted, it generates a master transaction using the command specified by PCI_Cmd[3:0]. This signal should be held active until all requested data are transferred on the PCI bus, and should be deactivated in the second clock cycle following the last data transfer on PCI (otherwise it is considered as requesting a new transaction). Address for master DMA writes. This address must always be valid from the beginning of a DMA write until the DMA write operation is completed. It should be incremented (by 4 bytes) each time data is transferred on PCI (Mst_Xfer_D1 is active). Address for master DMA reads. This address must always be valid from the beginning of a DMA read until the DMA read operation is completed. It should be incremented (by 4 bytes) each time data is transferred between the PCI core and the backend (Mst_RdData_Valid is active). Data for master DMA writes (to PCI bus). Byte enables for master DMA reads and writes. Active-low. When this signal is asserted, the core is notified that Mst_WrData[31:0] is valid in master write requests. If Mst_BE_Sel is active (high), it also means Mst_BE[3:0] is valid in both master write/read requests. Data receives acknowledge from the core for Mst_WrData[31:0] in master write requests, and Mst_BE[3:0] in both write/read requests if Mst_BE_Sel is active (high). This serves as the PUSH control for the internal FIFO and normally the POP control for the external FIFO in the backend which provides data and byte enables to the core.
PCI_Cmd[3:0]
I
Mst_Burst_Req
I
Mst_WrAd[31:0]
I
Mst_RdAd[31:0]
I
Mst_WrData[31:0] Mst_BE[3:0] Mst_WrData_Valid
I I I
Mst_WrData_Rdy
O
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QL5332 QuickPCI Data Sheet Rev. C
Table 1: QL5332 PCI32N Master Interface Signals (Continued)
Signal Type Description Byte enable select for master transactions. When low, Mst_BE[3:0] should remain unchanged throughout the entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO using Mst_WrData_Valid (along with data in case of a master write) is used. Should be held unchanged throughout the transaction. Requested master write transaction is completed. Active for only one clock cycle. Master read termination mode select when Mst_BE_Sel is high. When both Mst_BE_Sel and Mst_Rd_Term_Sel are high, master read termination happens when the internal FIFO is empty (out of byte enables). Mst_Two_Reads and Mst_One_Read (from backend) are ignored in this case. When either Mst_BE_Sel or Mst_Rd_Term_Sel is low, Mst_Two_Reads and Mst_One_Read are used to signal end of master read. Should be held unchanged throughout the transaction. This signals to the core that only one data transfer remains to be read in the burst read. Should be asserted after the backend receives the second last piece of data from the core. In the case of a single-data-phase master read request, it should be asserted at the time it makes the request. This signals to the core that only two data transfers remain to be read in the burst read. Should be asserted after the backend receives the third last piece of data from the core. It has no effect on single-data-phase master read requests. Master read data valid on Usr_Addr_WrData[31:0] from the core to the backend. This serves as the PUSH control for the external FIFO in the backend that receives data from the core. Requested master read transaction is completed. Active for only one clock cycle. Internal FIFO flush. The internal FIFO is flushed immediately after it is sampled active on the rising edge of a PCI clock. Not usually used. Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch). For full PCI compliance, this port should be always set to 1. Data was transferred on the PCI bus in the previous clock cycle in PCI32_25N-initiated master transactions. Useful for updating DMA transfer counts on DMA Read operations and for updating master write address on DMA Write operations. Active during the last data transfer of a master transaction. Copy of the PCI REQN signal generated by QL5332 as a PCI master. Not usually used in the backend design. Copy of the PCI IRDYN signal generated by QL5332 as a PCI master. Valid only when QL5332 is the PCI master. Kept high otherwise. Not usually used in the backend design. Target abort detected during master transaction. This is normally an error condition to be handled in the DMA controller. Target timeout detected (master abort, no response from target). This is normally an error condition to be handled in the DMA controller.
Mst_BE_Sel
I
Mst_WrBurst_Done
O
Mst_Rd_Term_Sel
I
Mst_One_Read
I
Mst_Two_Reads
I
Mst_RdData_Valid Mst_RdBurst_Done Flush_FIFO Mst_LatCntEn
O O I I
Mst_Xfer_D1 Mst_Last_Cycle Mst_REQN Mst_IRDYN Mst_Tabort_Det Mst_TTO_Det
O O O O O O
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QL5332 QuickPCI Data Sheet Rev. C
Target Interface Signals
The target interface signals for QL5332 PCI32N are shown in Table 2. Table 2: QL5332 PCI32N Target Interface Signals
Signal Type Description Target address and target write data. During all target accesses, the address is presented on Usr_Addr_WrData[31:0] at the same time Usr_Adr_Valid is active. During target write transactions, this port also presents valid write data to the PCI configuration space or user logic when Usr_Adr_Inc is active. During master read transactions, this port also presents valid data read from PCI to the backend. This is the registered version of the PCI AD[31:0] signal. PCI command and byte enables. During target accesses, the PCI command is presented on Usr_CBE[3:0] at the same time Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI configuration space or user logic. This is the registered version of the PCI CBEN[3:0] signal. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device memory or I/O space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal is low, indicating that the address is no longer on Usr_Addr_WrData[31:0]. This signal, when asserted, indicates that the target address should be incremented, because the previous data transfer has completed. During burst target accesses, the target address is only presented to the backend at the beginning of the transaction when Usr_Adr_Valid is active, and must therefore be latched and incremented (by 4) for subsequent data transfers. For target write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the state of Usr_Rdy). For read transactions, Usr_Adr_Inc signals to the backend that the core has presented the read data onto the PCI bus (has asserted TRDYN). This signal must be asserted by the backend when a user read command (e.g., Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc.) has been decoded from Usr_CBE[3:0]. It is acknowledged by the core only when Usr_Adr_Valid is active. This signal must be asserted by the backend when a user write command (e.g., Memory Write, Memory Write and Invalidate, I/O Write, etc.) has been decoded from Usr_CBE[3:0]. It is acknowledged by the core only when Usr_Adr_Valid is active. This signal must be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). This signal is acknowledged by the core only when Usr_Adr_Valid is active. This signal is active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at the beginning of the transaction. The write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a user write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc.
Usr_Addr_WrData[31:0]
O
Usr_CBE[3:0]
O
Usr_Adr_Valid
O
Usr_Adr_Inc
O
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write
O
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QL5332 QuickPCI Data Sheet Rev. C
Table 2: QL5332 PCI32N Target Interface Signals (Continued)
Signal Type Description This signal is active throughout a "configuration write" transaction. The write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. This signal is active throughout a "user read" transaction, which has been decoded by Usr_RdDecode at the beginning of the transaction. This signal is active throughout a "configuration read" transaction. Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the backend, required to be presented during user reads. Bits 3 from the Command Register in the PCI configuration space (offset 04h). Enable Special Cycle monitoring. If high, the core reports data parity error in Special Cycles through SERRN if Cfg_CmdReg8 is active. Bits 4 from the Command Register in the PCI configuration space (offset 04h). Memory Write and Invalidate (MWI) Enable. If high, the core can generate MWI transactions as requested by the backend. Otherwise it uses Memory Write instead even if MWI is requested. Note that there are also other conditions that limit whether MWI can be generated by the core. Bits 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error Response. If high, the core uses PERRN to report data parity errors. Otherwise the core always tristates PERRN. Bits 8 from the Command Register in the PCI configuration space (offset 04h). SERRN Enable. If high, the core uses SERRN to report address parity errors if Cfg_CmdReg6 is high. Otherwise the core always tristates SERRN. 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Upper 6 bits of the Cache Line Size register in the configuration space (offset 0Ch). The core always assumes that the lower two bits ([1:0]) of the Cache Line Size register to be "00". Used when a target read operation should return the value set on Mst_RdAd[31:0] instead of Usr_RdData[31:0]. This select pin saves on logic which would otherwise need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Used when a target read operation should return the value set on Mst_WrAd[31:0] instead of Usr_RdData[31:0]. This select pin saves on logic which would otherwise need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). System error asserted on the PCI bus. When this signal is active, the Signaled System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Data parity error detected on the PCI bus by the master. When this signal is active, bit 8 of the Status Register must be set in the PCI configuration space (offset 04h). Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within target accesses to the core.
Cfg_Write
O
Usr_Read Cfg_Read Cfg_RdData[31:0] Usr_RdData[31:0] Cfg_CmdReg3
O O I I I
Cfg_CmdReg4
I
Cfg_CmdReg6
I
Cfg_CmdReg8 Cfg_LatCnt[7:0] Cfg_CacheLineSize[7:2]
I I I
Usr_MstRdAd_Sel
I
Usr_MstWrAd_Sel
I
Cfg_PERR_Det
O
Cfg_SERR_Sig
O
Cfg_MstPERR_Det Usr_TRDY
O O
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QL5332 QuickPCI Data Sheet Rev. C
Table 2: QL5332 PCI32N Target Interface Signals (Continued)
Signal Usr_STOP Usr_DEVSEL Usr_Last_Cycle_D1 Type O O O Description Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only within target accesses to the core. Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within target accesses to the core. Active one clock cycle after the last data phase occurs on PCI. Active only for one clock cycle. Used to delay (add wait states to) a target PCI transaction when the backend needs additional time to provide data (read) or accept data (write). Subject to PCI latency restrictions if PCI compliance is needed. Used to prematurely stop a PCI target access. Used to signal Target Abort on PCI when the backend is unable to complete a transaction and does not want the master to retry. Rarely used.
Usr_Rdy Usr_Stop Usr_Abort
I I I
Internal PCI Signals
The internal PCI signals for QL5332 PCI32N are shown in Table 3. Table 3: QL5332 PCI32N Internal PCI Signals
Signal PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 PCI_GNTN_D1 Type O O O O O O O O O Description PCI clock. On a global clock network. Inverted and synchronized PCI reset signal. Active high. When the PCI reset is removed, this signal also goes from high to low but synchronized to the PCI clock. On a global clock network. Copy of the IRDYN signal from the PCI bus, delayed by one clock. Copy of the FRAMEN signal from the PCI bus, delayed by one clock. Copy of the DEVSELN signal from the PCI bus, delayed by one clock. Copy of the TRDYN signal from the PCI bus, delayed by one clock. Copy of the STOPN signal from the PCI bus, delayed by one clock. Copy of the IDSEL signal from the PCI bus, delayed by one clock. Copy of the GNTN signal from the PCI bus, delayed by one clock.
RAM Module Features
The QL5332 device has twelve 1,152-bit RAM modules, for a total of 13,824 RAM bits. Using two "mode" pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks (see Figure 3). The blocks are also easily cascadable to increase their effective width or depth. See Table 4 for RAM mode configurations.
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QL5332 QuickPCI Data Sheet Rev. C
Figure 3: RAM Module
RAM Module
MODE[1:0] WA[a:0] WD[w:0] ASYNCRD RA[a:0] RD[w:0]
WE WCLK
RE RCLK
Table 4: RAM Configurations
Mode 64x18 128x9 256x4 512x2 Address Buses [a:0] [5:0] [6:0] [7:0] [8:0] Data Buses [w:0] [17:0] [8:0] [3:0] [1:0]
The RAM modules are dual-ported, with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 512-deep configurations as large as 24 bits wide in the QL5332 device. A similar technique can be used to create depths greater than 512 words. In this case address signals higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
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QL5332 QuickPCI Data Sheet Rev. C
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5332 device. Six pins are dedicated to JTAG and programming functions on each QL5332 device, and are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM, is used only for programming.
Development Tools
Software support for the QL5332 device is available through the QuickWorks development package. QuickWorks is fully integrated into the Windows 98, 2000, NT, ME and XP operating systems. It provides design, layout, pre- and post-layout simulation and external stimulus design tools as shown in Figure 4. The program that links all these applications together and acts as the design flow manager is called Seamless pASIC Design Environment (SpDE). The term "pASIC" is a registered trademark of QuickLogic Corporation and refers to a QuickLogic FPGA, or "programmable ASIC." QuickWorks can be used to perform the following functions in the design process: * * * * * Design Pre-layout Simulation Synthesis Placement and Optimization Post-layout Simulation
The UNIX-based QuickTools package is a subset of QuickWorks and provides a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools reads EDIF netlists and provides support for all QuickLogic devices. QuickTools also supports a wide range of thirdparty modeling and simulation tools.
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QL5332 QuickPCI Data Sheet Rev. C
Figure 4: QuickWorks Design Flow
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QL5332 QuickPCI Data Sheet Rev. C
QL5332 External Device Pins
Table 5 describes the different types of devices pins. Table 6 describes the external pins on the QL5332 device, some of which connect to the PCI bus, and others that are programmable as user IO. Table 5: Pin Types
Type IN OUT T/S S/T/S O/D Input. A standard input-only signal Totem pole output. A standard active output driver Tri-state. A bi-directional, tri-state input/output pin Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central resource to sustain the inactive state once the active driver has released the signal. Open Drain. Allows multiple devices to share this pin as a wired-or. Description
Table 6: QL5332 External Device Pins
Pin/Bus Name VCC VCCIO GND I/O GLCK/I ACLK/I TDI/RSIa TDO/RCOa TCK TMS TRSTB/RROa STM AD[31:0] CBEN[3:0] PAR FRAMEN DEVSELN CLK RSTN Type IN IN IN T/S IN IN IN OUT IN IN IN IN T/S T/S T/S S/T/S Supply Pin. Tie to 3.3V supply. Supply Pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O. Ground Pin. Tie to GND on the PCB. Programmable Input/Output/Tri-State/Bi-directional Pin. Programmable Global Network or Input-Only Pin. Tie to VCC or GND if unused. Programmable Array Network or Input-Only Pin. Tie to VCC or GND if unused. JTAG Data In/RAM Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data for RAM init. JTAG Data Out/RAM Init. Clock. Leave unconnected if unused. Connect to Serial EPROM clock for RAM init. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for RAM init. QuickLogic Reserved Pin. Tie to GND on the PCB. PCI Address and Data. 32 bit multiplexed address/data bus. PCI Bus Command and Byte Enables. Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity. Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. Master drives PAR on address cycles and PCI writes. The Target drives PAR on PCI reads. PCI Cycle Frame. Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction. PCI System Clock Input. PCI System Reset Input. Function
S/T/S PCI Device Select. Driven by a Target that has decoded a valid base address. IN IN
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QL5332 QuickPCI Data Sheet Rev. C
Table 6: QL5332 External Device Pins (Continued)
REQN GNTN PERRN SERRN IDSEL IRDYN TRDYN STOPN INTAN T/S IN S/T/S O/D IN S/T/S S/T/S PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) needs to use the bus. A point-to-point signal between the PCI device and the System Arbiter. PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI bus by the Arbiter. A point-to-point signal between the PCI device and the System Arbiter. PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BEN busses. PCI System Error. Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select. Use to select a specific PCI Agent during System Initialization. PCI Initiator Ready. Indicates the Initiator's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready. Indicates the Target's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. Interrupt A. Asynchronous Active-Low Interrupt Request.
S/T/S PCI Stop. Used by a PCI Target to end a burst transaction. O/D
a. See Quick Note 65 at http://quicklogic.com/images/quicknote65.pdf for information on RAM initialization.
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QL5332 QuickPCI Data Sheet Rev. C
Electrical Specifications
DC Characteristics
The DC Specifications are provided in Table 7 through Table 9. Table 7: Absolute Maximum Ratings
Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO + 0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to + 150C 300 C
Table 8: Operating Range
Symbol VCC VCCIO TA K Parameter Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Delay Factor -A Speed Grade Industrial Min 3.0 3.0 -40 0.43 Max 3.6 5.5 85 0.90 Commercial Min 3.0 3.0 0 0.46 Max 3.6 5.25 70 0.88 V V C n/a Unit
Table 9: DC Characteristics
Symbol VIH VIL VOH VOL Il IOZ CI IOS ICC ICCIO Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitancea Output Short Circuit Currentb D.C. Supply Currentc D.C. Supply Current on VCCIO IOH = -12 mA IOH = -500 A IOL = 16 mA IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VI.VIO = VCCIO or GND -10 -10 -15 40 0.50 typ. 0 Conditions Min 0.5 VCC -0.5 2.4 0.9 VCC 0.45 0.1 VCC 10 10 10 -180 210 2 100 Max VCCIO+ 0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A
a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -A commercial grade device only. Maximum ICC is 3 mA for all industrial grade devices. For AC conditions, contact QuickLogic Customer Engineering. * * * *
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QL5332 QuickPCI Data Sheet Rev. C
AC Characteristics
The AC Specifications (at VCC = 3.3 V, TA = 25 C (K = 1.00)) are provided in Table 10 through Table 17. (To calculate delays, multiply the appropriate K factor in Table 8 operating ranges by the following numbers.) Table 10: Logic Cells
Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay of the longest path: time taken by the combinatorial circuit to outputb Setup time: time the synchronous input of the flip-flop must be stable before the active clock edgeb Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-Q delay: the amount of time taken by the flipflop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low 1.4 1.8 0.0 0.8 1.6 1.6 1.4 1.2 1.9 1.8 Propagation Delays (ns) Fanouta 2 1.7 1.8 0.0 1.1 1.6 1.6 1.7 1.5 1.9 1.8 3 2.0 1.8 0.0 1.4 1.6 1.6 2.0 1.8 1.9 1.8 4 2.3 1.8 0.0 1.7 1.6 1.6 2.3 2.1 1.9 1.8 8 3.5 1.8 0.0 2.9 1.6 1.6 3.5 3.3 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3 V and TA=25xC. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. b. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5332 QuickPCI Data Sheet Rev. C
Table 11: RAM Cell Synchronous Write Timing
Symbol Parameter 1 tSWA WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 1.0 Propagation Delays (ns) Fanouta 2 1.0 3 1.0 4 1.0 8 1.0
tHWA
0.0
0.0
0.0
0.0
0.0
tSWD tHWD tSWE
1.0
1.0
1.0
1.0
1.0
0.0
0.0
0.0
0.0
0.0
1.0
1.0
1.0
1.0
1.0
tHWE
0.0
0.0
0.0
0.0
0.0
tWCRD
5.0
5.3
5.6
5.9
7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3 V and TA=25xC. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 12: RAM Cell Synchronous Read Timing
Symbol Parameter 1 tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to RCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to RCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RDa 1.0 0.0 1.0 0.0 4.0 Propagation Delays (ns) Fanout 2 1.0 0.0 1.0 0.0 4.3 3 1.0 0.0 1.0 0.0 4.6 4 1.0 0.0 1.0 0.0 4.9 8 1.0 0.0 1.0 0.0 6.1
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular design.
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QL5332 QuickPCI Data Sheet Rev. C
Table 13: RAM Cell Synchronous Read Timing
Symbol Parameter 1 rPDRD RA to RD: time between when the READ ADDRESS is input and when the DATA is outputa 3.0 Propagation Delays (ns) Fanout 2 3.3 3 3.6 4 3.9 8 5.1
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular design.
Table 14: Input-Only Cells
Symbol tIN tINI tISU Parameter 1 High drive input delay High drive input, inverting delay Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-Q Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge 1.5 1.6 3.1 2 1.6 1.7 3.1 Propagation Delays (ns) Fanouta 3 1.8 1.9 3.1 4 1.9 2.0 3.1 8 2.4 2.5 3.1 12 2.9 3.0 3.1 24 4.4 4.5 3.1
tIH tICLK tIRST tIESU tIEH
0.0 0.7 0.6
0.0 0.8 0.7
0.0 1.0 0.9
0.0 1.1 1.0
0.0 1.6 1.5
0.0 2.1 2.0
0.0 3.6 3.5
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular design.
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QL5332 QuickPCI Data Sheet Rev. C
Table 15: Clock Cells
Symbol tACK tGCKP tGCKB Parameter 1 Array clock delay Global clock pin delay Global clock buffer delay 1.2 0.7 0.8 2 1.2 0.7 0.8 Propagation Delays (ns) Fanouta 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 12 1.7 0.7 1.3 15 1.8 0.7 1.4
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
Table 16: I/O Cell Input Delays
Symbol tI/O tISU tIH tIOCLK tIORST tIESU tIEH Parameter 1 Input delay (bidirectional pad) Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-Q Input register reset delay: time between when the flip-flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge 1.3 3.1 0.0 0.7 0.6 Propagation Delays (ns) Fanouta 2 1.6 3.1 0.0 1.0 0.9 3 1.8 3.1 0.0 1.2 1.1 4 2.1 3.1 0.0 1.5 1.4 8 3.1 3.1 0.0 2.5 2.4 10 3.6 3.1 0.0 3.0 2.9
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
2.3 0.0
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular design.
Table 17: I/O Cell Output Delays
Symbol tOUTLH tOUTHL tPZH Parameter Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Propagation Delays (ns) Output Load Capacitance (pF) 30 2.1 2.2 1.2 50 2.5 2.6 1.7 75 3.1 3.2 2.2 100 3.6 3.7 2.8 150 4.7 4.8 3.9
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QL5332 QuickPCI Data Sheet Rev. C
Table 17: I/O Cell Output Delays
Symbol tPZL tPHZ tPLZ Parameter Output Delay tri-state to low (10% of L) Output Delay high to tri-State Output Delay low to tri-State
a a
Propagation Delays (ns) Output Load Capacitance (pF) 30 1.6 2.0 1.2 50 2.0 75 2.6 100 3.1 150 4.2
a. The following loads are used for tPXZ:
tPHZ 1K 5 pF 1K tPLZ 5 pF
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(c) 2004 QuickLogic Corporation
QL5332 QuickPCI Data Sheet Rev. C
QL5332 - 208 PQFP Pinout Diagram
Figure 5: 208-pin PQFP PIN #157
PIN #1
QuickPCI QL5332-33APQ208C
PIN #53
PIN #105
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QL5332 QuickPCI Data Sheet Rev. C
QL5332 - 208 PQFP Pinout Table
Table 18: QL5332 - 208 PQFP Pinout Table
PQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 FUNCTION I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND INTAN RSTN ACLK/I VCC GCLK/I CLK VCC GNTN REQN AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] VCC CBEN[3] PQ208 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FUNCTION GND IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] CBEN[2] TDI FRAMEN IRDYN TRDYN DEVSELN GND STOPN VCC I/O I/O PERRN I/O SERRN PAR CBEN[1] AD[15] AD[14] AD[13] AD[12] GND AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] VCCIO AD[4] PQ208 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 FUNCTION AD[3] AD[2] AD[1] AD[0] I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PQ208 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 FUNCTION GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O PQ208 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 FUNCTION I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
Summary: 50 PCI pins, 118 user I/O, 4 GCLK, and 2 ACLK.
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(c) 2004 QuickLogic Corporation
QL5332 QuickPCI Data Sheet Rev. C
QL5332 - 256 PBGA Pinout Diagram
Figure 6: 256-pin PBGA PIN #A1 Corner
A B C D E F G H J K L
20
19 18
17 16
15 14
13 12
11 10
9
8
7
6
5
4
3
2
1
Bottom View
M N P R T U V W Y
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QL5332 QuickPCI Data Sheet Rev. C
QL5332 - 256 PBGA Pinout Table
Table 19: QL5332 - 256 PBGA Pinout Table
PB256 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC STM NC I/O I/O I/O I/O PB256 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 Function I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O GND I/O I/O VCC I/O GND I/O VCC I/O GND I/O I/O I/O NC I/O I/O I/O I/O I/O PB256 E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 K20 L1 Function I/O I/O I/O I/O I/O VCC VCC NC I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O NC I/O NC I/O I/O GCLK / I I/O I/O I/O VCC GCLK/I ACLK/I GCLK/I NC CLK PB256 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 Function ACLK/I RSTN GCLK/I VCC I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O VCC VCC I/O I/O I/O NC I/O I/O NC PB256 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 Function I/O I/O NC I/O I/O I/O I/O GND AD[26] VCC AD[22] GND FRAMEN VCC I/O I/O GND AD[11] VCC AD[4] GND I/O I/O I/O I/O NC I/O AD[30] AD[28] AD[24] IDSEL AD[18] AD[16] TRDYN STOPN VCCIO AD[15] AD[13] CBEN[0] AD[6] AD[2] I/O TMS PB256 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Function I/O I/O I/O TDI GNTN AD[27] CBEN[3] AD[21] AD[20] CBEN[2] DEVSELN PERRN CBEN[1] PAR AD[10] AD[9] AD[5] AD[1] AD[0] I/O TRSTB INTAN NC REQN AD[31] AD[29] AD[25] AD[23] AD[19] AD[17] IRDYN I/O SERRN AD[14] AD[12] AD[8] AD[7] AD[3] I/O I/O NC
Summary: 50 PCI pins, 148 user I/O, 4 GCLK, and 2 ACLK.
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QL5332 QuickPCI Data Sheet Rev. C
Contact Information
Phone: (408) 990-4000 (US) (416) 497-8884 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales
Support: www.quicklogic.com/support Internet: www.quicklogic.com
Revision History
Revision Rev. A Rev. B Rev. C Date December 2000 March 2001 July 2004 Bernhard Andretzky and Kathleen Murchek Converted to new format. Added Summary to pinout tables. Originator and Comments
Copyright and Trademark Information
Copyright (c) 2004 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
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